全部 标题 作者
关键词 摘要

OALib Journal期刊
ISSN: 2333-9721
费用:99美元

查看量下载量

相关文章

更多...

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

DOI: 10.4236/cs.2016.79210, PP. 2437-2442

Keywords: Delay-Locked Loop, Single Event Transients, Error Correction Circuit

Full-Text   Cite this paper   Add to My Lib

Abstract:

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.

References

[1]  Maillard, P., Holman, W.T., Loveless, T.D., Bhuva, B.L. and Massengill, L.W. (2010) An RHBD Technique to Mitigate Missing Pulses in Delay Locked Loops. IEEE Transactions on Nuclear Science, 57, 3634-3639.
http://dx.doi.org/10.1109/tns.2010.2087357
[2]  Sengupta, R., Vermeire, B., Clark, L.T. and Bakkaloglu, B. (2010) A 133 MHz Radiation-Hardened Delay-Locked Loop. IEEE Transactions on Nuclear Science, 57, 3626-3633.
http://dx.doi.org/10.1109/tns.2010.2086485
[3]  Maillard, P., Holman, W.T., Loveless, T.D. and Massengill, L.W. (2013) A New Error Correction Circuit for Delay Locked Loops. IEEE Transactions on Nuclear Science, 60, 4387-4393.
http://dx.doi.org/10.1109/tns.2013.2288103
[4]  Stoj?ev, M. and Jovanovi?, G. (2008) Clock Aligner Based on Delay Locked Loop with Double Edge Synchronization. Microelectronics Reliability, 48, 158-166.
http://dx.doi.org/10.1016/j.microrel.2007.02.025
[5]  Kao, S.-K., Chen, B.-J. and Liu, S.-I. (2007) A 62.5-625-Mhz Anti-Reset All-Digital Delay-Locked Loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 566-570.
http://dx.doi.org/10.1109/tcsii.2007.895326
[6]  Adell, P., Schrimpf, R. D., Barnaby, H. J., Marec, R., Chatry, C., Calvel, P., Barillot, C. and Mion, O. (2000) Analysis of Single-Event Transients in Analog Circuits. IEEE Transactions on Nuclear Science, 47, 2616-2623.
http://dx.doi.org/10.1109/23.903817
[7]  Naseer, R., Boulghassoul, Y., Draper, J., DasGupta, S. and Witulski, A. (2007) Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. Proceeding of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, 27-30 May 2007, 1879-1882.
[8]  Messenger, G.C. (1982) Collection of Charge on Junction Nodes from Ion Tracks. IEEE Transactions on Nuclear Science, 29, 2024-2031.
http://dx.doi.org/10.1109/tns.1982.4336490
[9]  Wirth, G.I., Vieira, M.G., Neto, E.H. and Kastensmidt, F.L. (2008) Modeling the Sensitivity of CMOS Circuits to Radiation Induced Single Event Transients. Microelectronics Reliability, 48, 29-36.
http://dx.doi.org/10.1016/j.microrel.2007.01.085
[10]  Loveless, T.D., Massengill, L.W., Bhuva, B.L., Holman, W.T., Casey, M.C., Reed, R.A. and Melinger, J.S. (2008) A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed- Signal Phase-Locked Loops. IEEE Transactions on Nuclear Science, 55, 3447-3455.
http://dx.doi.org/10.1109/tns.2008.2005677

Full-Text

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133