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Mathematical models and simulations of phase noise in phase-locked loops
Sethapong Limkumnerd,Duangrat Eungdamrong
Songklanakarin Journal of Science and Technology , 2007,
Abstract: Phase noises in Phase-Locked Loops (PLLs) are a key parameter for communication systems that contribute the bit-rate-error of communication systems and cause synchronization problems. Accurate predictions of phase noises through mathematical models are consequently desirable for practical designs of PLLs. Despite many phase noise models derived from noise sources from electronic devices such as an oscillator and a multiplier have been proposed, no phase noise models that include noises from loop filters have specifically been investigated. This paper therefore investigates the roles of loop filters in phase noise contribution. The major scopes of this paper is a detailed analysis and simulations of phase noise models resulting from all components. i.e. a voltage-controlled oscillator, a multiplier and a filter. Two particular second-order passive and active low-pass filters are compared. The results show that simulations of phase noises without an inclusion of filter noises may not be accurate because the filter noises, particularly the active filter, significantly contribute the total phase noise. Moreover, the passive filter does not significantly dominate the phase noise at low offset frequency while the active filters entirely dominate. Therefore, the passive filter is a more efficient filter for PLL circuit at low offset frequency. The phase noise models presented in this paper are relatively simple and can be used for accurate phase noise prediction for PLL designs.
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops  [PDF]
Jun Zhao,Yong-Bin Kim
VLSI Design , 2010, DOI: 10.1155/2010/946710
Abstract: A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32?nm Predictive Technology Model (PTM) at 0.9?V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700?MHz with less than 67?ps peak-to-peak jitter. The DCO consumes 2.2?mW at 650?MHz with 0.9?V power supply. 1. Introduction Phase-locked loops are widely used in many communication systems for clock and data recovery or frequency synthesis [1–5]. Cellular phones, computers, televisions, radios, and motor speed controllers are just a few examples that rely on PLLs for proper operation. With such a broad range of applications, PLLs have been extensively studied in literature. The conventional PLLs are often designed using analog approaches. However, analog PLLs have to overcome the digital switch noise coupled with power through power supply as well as substrate-induced noise. In addition, the analog PLL is very sensitive to process parameters and must be redesigned if the process is changed or migrates to next generation process. Although many approaches have been developed to improve the jitter performance, it often results in long lock-in time and increasing design complexity. With the increasing performance and decreasing cost of digital VLSI design technology, all digital phase-locked loops have become more attractive. Although ADPLL will not have the same performance as its analog counterpart, it provides a faster lock-in time and better testability, stability, and portability over difference process [6, 7]. The controlled oscillator is a key component in PLL, which is a replacement of the conventional voltage or current controlled oscillator in the fully digital PLLs. They are more flexible and usually more robust than the conventional VCO. Furthermore, the design compromise for the frequency gain in voltage or current controlled oscillator is not necessary in
Implementations of DPDE for Delay Locked Loop for High Frequency Clock of 2.5GHz High Speed Applications  [PDF]
J.Meenakshi,G. Rakesh Chowdary,A.L.G.N.Aditya
International Journal of Soft Computing & Engineering , 2012,
Abstract: Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Variable delay elements have many applications in VLSI circuits. They are extensively used in digital delay locked loops phase locked loops (PLLs), digitally controlled oscillators (DCOs), and microprocessor and memory circuits. In all these circuits, the variable delay element is one of the key building blocks. Its precision directly affects the overall performance of the circuit. In this a new proposed digitally controlled delay element is implemented in 130nm technology for DLL Delay locked loop for higher clock rates greater than 2.5GHz. This is implemented in Micro wind tool.
Temperature dependence of irradiation hardening due to dislocation loops and precipitates in RPV steels and model alloys  [PDF]
S. Kotrechko,V. Dubinko,N. Stetsenko,D. Terentyev,Xinfu He
Physics , 2014, DOI: 10.1016/j.jnucmat.2015.04.014
Abstract: A relative contribution to irradiation hardening caused by dislocation loops and solute-rich precipitates is established for RPV steels of WWER-440 and WWER-1000 reactors, based on TEM measurements and mechanical testing at reactor operating temperature of 563 K. The pinning strength factors evaluated for loops and precipitates are shown to be much lower than those obtained for model alloys based on the room temperature testing as well as those evaluated by means of atomistic simulations in the temperature range of 300 to 600 K. This discrepancy is explained in the framework of a model of thermally activated dislocation motion, which takes into account the difference in temperature and strain rate employed in atomistic simulations and in mechanical testing.
Identification of Vibration Parameters in a Spacecraft using Kalman Filters, Numerical Search and Phase-Locked Loops
Aage Skullestad
Modeling, Identification and Control , 2000, DOI: 10.4173/mic.2000.2.1
Abstract: Communication in space requires antennas that are accurately pointed. Often antennas are mounted on lightly damped space structures, that are easily set into vibration, which decreases the pointing accuracy of the antennas. Knowing the vibration frequencies simplifies the control tasks and may also improve the pointing accuracy. This paper describes identification of vibration frequencies in a space structure, based on frequency weighted Kalman filters, a Gauss-Newton numerical search method and phase-locked loops.
Models for Master-Slave Clock Distribution Networks with Third-Order Phase-Locked Loops  [PDF]
José Roberto Castilho Piqueira,Marcela de Carvalho Freschi
Mathematical Problems in Engineering , 2007, DOI: 10.1155/2007/18609
Abstract: The purpose of this work is to study the processing and transmission of clock signals in networks of geographically distributed nodes, in order to derive conditions for frequency and phase synchronization between the nodes. The focus is on the master-slave architecture, which presents a priority scheme of clock distribution. One-way master-slave (OWMS ) and two-way master-slave (TWMS) chains are studied, considering that the slave nodes are third-order phase-locked loops (PLLs). Third-order PLLs are chosen to improve the transient response but, if their parameters are not well adjusted, stability problems and chaotic behaviors appear, restricting the lock-in range of the network. Lock-in range for third-order PLLs with Sallen-Key filter is determined and it is verified whether this range is reduced when the PLLs are connected to a network. Numerical experiments show how chain size changes the lock-in ranges and the acquisition times.
Phase-Locked Signals Elucidate Circuit Architecture of an Oscillatory Pathway  [PDF]
Andreja Jovic,Bryan Howell,Michelle Cote,Susan M. Wade,Khamir Mehta,Atsushi Miyawaki,Richard R. Neubig,Jennifer J. Linderman ,Shuichi Takayama
PLOS Computational Biology , 2010, DOI: 10.1371/journal.pcbi.1001040
Abstract: This paper introduces the concept of phase-locking analysis of oscillatory cellular signaling systems to elucidate biochemical circuit architecture. Phase-locking is a physical phenomenon that refers to a response mode in which system output is synchronized to a periodic stimulus; in some instances, the number of responses can be fewer than the number of inputs, indicative of skipped beats. While the observation of phase-locking alone is largely independent of detailed mechanism, we find that the properties of phase-locking are useful for discriminating circuit architectures because they reflect not only the activation but also the recovery characteristics of biochemical circuits. Here, this principle is demonstrated for analysis of a G-protein coupled receptor system, the M3 muscarinic receptor-calcium signaling pathway, using microfluidic-mediated periodic chemical stimulation of the M3 receptor with carbachol and real-time imaging of resulting calcium transients. Using this approach we uncovered the potential importance of basal IP3 production, a finding that has important implications on calcium response fidelity to periodic stimulation. Based upon our analysis, we also negated the notion that the Gq-PLC interaction is switch-like, which has a strong influence upon how extracellular signals are filtered and interpreted downstream. Phase-locking analysis is a new and useful tool for model revision and mechanism elucidation; the method complements conventional genetic and chemical tools for analysis of cellular signaling circuitry and should be broadly applicable to other oscillatory pathways.
Broadband suppression of phase-noise with cascaded phase-locked-loops for the generation of frequency ramps  [PDF]
T. Musch
Advances in Radio Science : Kleinheubacher Berichte , 2003,
Abstract: The generation of analogue frequency ramps with non-fractional phase-locked-loops (PLL) is a cost effective way of linearising varactor controlled oscillators (VCO). In case that the VCO shows a high phase-noise level, a single non-fractional PLL is not able to suppress the phase-noise of the VCO sufficiently. The reason for this is the limited loopbandwidth of the PLL. In the field of precise measurements a high phase-noise level is mostly not tolerable. Examples of VCO-types with an extremely high phase noise level are integrated millimetre wave oscillators based on GaAs-HEMT technology. Both, a low quality factor of the resonator and a high flicker-noise corner frequency of the transistors are the main reason for the poor phase-noise behaviour. On the other hand this oscillator type allows a cost effective implementation of a millimetre-wave VCO. Therefore, a cascaded two-loop structure is presented that is able to linearise a VCO and additionally to reduce its phase-noise significantly.
Controller Design for Synchronizing Distributed Generation Systems with the Phase Locked Loop (PLL)  [PDF]
Seyyed Zynolabedin Mousavi,Parviz Amiri,Seyyed Ahmad Hoseini
International Journal of Engineering and Advanced Technology , 2012,
Abstract: In this paper a fuel cell power plant design using phase locked loop method for paralleling a fuel cell with the global network is described. Despite the fact that synchronous systems for scattering generation sources like generators have been used in Iran’s plants, but there has been made fewer efforts in the case of plants based on fuel cell. In this paper an approach is presented for synchronization based on PLL that can reduce the response time to less than 2 seconds and time difference becomes zero in less than 3 seconds. Using the relay auto tuning algorithm in the closed loop system, the frequency fluctuations become less than 0.05% at the output. As in this approach, tuning is based on the DC voltage level, the induction property that makes the PID controller be unstable is reduced and we will have a very stable output wave. This is the main advantage of this controller. Presented control structure is made up of three loops, whichwe will reached frequency to reference frequency by use of first loop and in the next loop we do it’s phasecontrol whit take an integration of frequency, and in the frequencies difference less than 1 Hz. Presented control structure is made up of three loops. Using first loop, the frequency is reached near the reference value and in the next loop the phase is controlled by integration of the frequency, and in the frequency differences less than 1 Hz, the third loops does control frequency in independent way from the phase. Another advantage of this method is that the circuit remains in phase locked state when the phase has been synchronized, and there is no need to consider the time of connection to the network, and finally the output fluctuation is brought into zero. In this paper, it is also built an empirical example of digital synchronizer which is efficient in synchronizing distributed generation systems with the phase locked loop and will be described in detail in continuation.
Design of loop filter for high order charge-pump phase-locked loops
高阶电荷泵锁相环环路滤波器的设计

ZHAO Yi-bo,FENG Jiu-chao,
赵益波
,冯久超

控制理论与应用 , 2011,
Abstract: Considering the characteristics of discrete-time sampling for charge-pump phase-locked loops(CPPLLs), we propose a blocking design method for loop filter in high order CPPLLs. By this method, the CPPLL of any optional order and type can be derived, and phase jitters can be eliminated. Also, high frequency step input or ramp input can be tracked. By analyzing the stability and characteristics of CPPLLs, the range of the candidate loop parameters can be determined, from which the obtained CPPLLs of n-th order and n type are superior to others. Effectiveness of the design method and correctness of the analysis method are validated by the simulations of two types of CPPLLs. The proposed method provides an important reference and guideline for the design of high order CPPLLs Loop filters.
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