In this work, we show that
an excessive lattice heating problem can occur in the diode electrostatic
discharge (ESD) protection device connected to a VDD？bus in the popular diode input protection
scheme, which is favorably used in CMOS RF ICs. To figure out the reason for
the excessive lattice heating, we construct an equivalent circuit for input
human-body model (HBM) test environment of a CMOS chip equipped with the diode
protection circuit, and execute mixed-mode transient simulations utilizing a
2-D device simulator. We analyze the simulation results in detail to show out
that a parasitic pnp bipolar transistor action relating nearby p+-substrate
contacts is responsible for the excessive lattice heating in the diode
protection device, which has never been focused before anywhere.
References
[1]
Leroux, P. and Steyaert, M. (2001) High-Performance 5.2GHz LNA with On-Chip Inductor to Provide ESD Protection. Electronics Letters, 37, 467-469. http://dx.doi.org/10.1049/el:20010271
[2]
Chatterjee, A. and Polgreen, T. (1991) A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads. IEEE Electron Device Letters, 12, 21-22. http://dx.doi.org/10.1109/55.75685
[3]
Worley, E.R., Gupta, R., Jones, B., Kjar, R., Nguyen, C. and Tennyson, M. (1995) Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions. Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Phoenix, 12-14 September 1995, 13-20. http://dx.doi.org/10.1109/eosesd.1995.478263
[4]
Yeh, C.-T., Ker, M.-D. and Liang, Y.C. (2010) Optimization of Layout Style of ESD Protection Diode for Radio- Frequency Front-End and High-Speed I/O Interface Circuits. IEEE Transactions on Device and Materials Reliability, 10, 238-246. http://dx.doi.org/10.1109/TDMR.2010.2043433
[5]
Yang, M.-T., Du, Y., Teng, C., Chang, T., Worley, E., Liao, K., Yau, Y.-W. and Yeap, G. (2010) BSIM4-Based Lateral Diode Model for LNA Co-Designed with ESD Protection Circuit. 11th International Symposium on Quality Electronic Design (ISQED), San Jose, 22-24 March 2010, 87-91.
[6]
Au, T. and Syrzycki, M. (2013) Investigation of STI Diodes as Electrostatic Discharge (ESD) Protection Devices in Deep Submicron (DSM) CMOS Process. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Regina, SK, 5-8 May 2013, 1-5.
[7]
Feng, H., Chen, G., Zhan, R., Wu, Q., Guan, X., Xie, H. and Wang, A.Z.H. (2003) A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology. IEEE Journal of Solid-State Circuits, 38, 995-1006. http://dx.doi.org/10.1109/JSSC.2003.811978
[8]
Fankhauser, B. and Deutschmann, B. (2004) Using Device Simulations to Optimize ESD Protection Circuits. International Symposium on Electromagnetic Compatibility, 9-13 August 2004, Vol. 3, 963-968. http://dx.doi.org/10.1109/isemc.2004.1349956
[9]
Choi, J.Y. (2010) A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode. Communications and Network, 2, 11-25. http://dx.doi.org/10.4236/cn.2010.21002
[10]
ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005.
[11]
Amerasekera, A., van Roozendaal, L., Bruines, J. and Kuper, F. (1991) Characterization and Modeling of Second Breakdown in nMOST’s for Extraction and ESD-Related Process and Design Parameters. IEEE Transactions on Electron Devices, 38, 2161-2168. http://dx.doi.org/10.1109/16.83744
