Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm. 1. Introduction With the ever increasing complexity of system on chip circuits, the software and hardware developers can no longer wait for the fabrication phase to test their designs . Currently, it is estimated that 60 to 80 percent of an ASIC design is spent in performing verification . FPGA-based prototyping is an important step in the creation of the final product and it is the key to the success of marketing in time. The key advantage of FPGA-based prototyping is the ability to run at high speed (sometimes at almost real-time speed) a cycle-accurate, bit-accurate model of the SoC . The availability of automatic FPGA mapping tools has streamlined the design conversion process, making the path from ASIC design to FPGA implementation more straightforward. When the logic capacity of a single FPGA is less than the size of the design under test, a multi-FPGA platform is used to map the entire design. Because the silicon area overhead of FPGA versus ASIC technology has been measured to be about 40x , FPGA programming technology requires that an ASIC logic design be partitioned across multiple FPGA devices to achieve the necessary device logic capacity. The number of FPGAs depends on the size of the prototyping system, ranging from a few  up to 60 FPGAs . In order to map the design into a multi-FPGA board, a partitioning tool decomposes the design into pieces that will fit within the logic resources of individual FPGA devices. Partitioning is often performed to
H. Krupnova, “Mapping multi-million gate SoCs on FPGAs: industrial methodology and experience,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 1236–1241, February 2004.
S. Asaad, R. Bellofatto, B. Brezzo et al., “A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation,” in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '12), pp. 153–162, February 2012.
J. Babb, R. Tessier, M. Dahl, S. Z. Hanono, D. M. Hoki, and A. Agarwal, “Logic emulation with virtual wires,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 6, pp. 609–626, 1997.
L. McMurchie and C. Ebeling, “PathFinder: a negotiation-based performance-driven router for FPGAs,” in Proceedings of the International Workshop on Field Programmable Gate Array, pp. 111–117, February 1995.
X. Song, W. N. N. Hung, A. Mishchenko, M. Chrzanowska-Jeske, A. Kennings, and A. Coppola, “Board-level multiterminal net assignment for the partial cross-bar architecture,” IEEE Transactions on Very Large Scale Integration ystems, vol. 11, no. 3, pp. 511–513, 2003.
W. Mak and D. F. Wong, “On optimal board-level routing for FPGA-based logic emulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 282–289, 1997.
J. Babb, R. Tessier, and A. Agarwal, “Virtual wires: overcoming pin limitations in FPGA-based logic emulators,” in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines (FCCM '93), pp. 142–151, April 1993.
R. Tessier, J. Babb, M. Dahl, et al., “The virtual wires emulation system: a gate-efficient ASIC prototyping environement,” in Proceedings of the International Workshop on Field-Programmable Gate Array, ACM, Berkeley, Calif, USA, February 1994.
M. Inagi, Y. Takashima, Y. Nakamura, and A. Takahashi, “Optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA prototyping systems,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences A, vol. E91, no. 12, pp. 3539–3547, 2008.
M. Inagi, Y. Takashima, and Y. Nakamura, “Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems,” in Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FLP '09), pp. 212–217, September 2009.
M. Turki, Z. Marrakchi, H. Mehrez, and M. Abid, “Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform,” in Proceedings of the 9th international conference on Reconfigurable Computing (ARC '13), Los Angeles, Calif, USA, March 2013.
M. Turki, Z. Marrakchi, H. Mehrez, and M. Abid, “Towards synthetic benchmarks generator for CAD tool evaluation,” in Proceedings of the 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME '12), 2012.