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An Effective Verification and Validation Strategy for Safety-Critical Embedded Systems

Keywords: Veri fication and Validation process , safety , critical systems , embedded systems , reliability

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This paper presents the best practices to carry out the verification and validation (V&V) for a safety-critical embedded system, part of a larger system-of-systems. The paper talks about the effectiveness of thisstrategy from performance and time schedule requirement of a project. The best practices employed fortheV &Vis a modification of the conventional V&V approach. The proposed approach is iterative whichintroduces new testing methodologies apart from the conventional testing methodologies, an effective wayof implementing the phases of the V&V and also analyzing the V&V results. The new testing methodologiesinclude the random and non-real time testing apart from the static and dynamic tests. The process phasesare logically carried out in parallel and credit of the results of the different phases are takento ensure thatthe embedded system that goes for thefield testing is bug free. The paper also demonstrates the iterativequalities of the process where the iterations successivelyfind faults in the embedded system and executingthe process within a stipulated time frame, thus maintaining the required reliability of the system. Thisapproach is implemented in the most critical applications—-aerospace application where safety of thesystem cannot be compromised. The approach used afixed number of iterationswhich is set to4in thisapplication, with each iteration adding to the reliability and safety of the embedded system. Data collectedand results observed are compared with a conventional approach for the same application and it isdemonstrated that the strategy proposed reduces the time taken by 50% as compared to a conventionalprocess that attains the same reliability as required in the stipulated time


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