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Countermeasures Against DPA Attacks on FPGA Implementation of AES

Keywords: AES , side channel attack , different power analysis , register swapping , random pre-charging

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Even a highly secured algorithm that proves to be mathematically secured has a possibility to leak secret information, like key, thus stored while implementing them in hardware platform. This study focuses on the necessity to prevent such leakage by making some changes in the algorithm in such a way that the functionality of the algorithm is unaltered thereby assuring the possibility of attacks are greatly reduced. This study discusses the Field Programmable Gate Array (FPGA) implementation of the Advanced Encryption Standard (AES) with countermeasures against Differential Power Analysis (DPA) attacks. The study proposes two different countermeasure methods: register swapping and random recharging. As a result, it shows that these countermeasures increase the complexity of attack.


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