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Design of Multiple Master ASIC Interconnect

Keywords: SoC design , OCP protocol , VHDL language , AXI protocol , IP Core

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System on Chip is composed of many Intellectual Property (IP) blocks which communicate with each other using different bus protocols. Each IP may have different native protocol. So establishing communication between these bus protocols which vary from one IP to another is of much significance. The protocols used may be either proprietary or non-proprietary. AXI 1.0 and OCP 2.0 protocols and are used to build our ASIC interconnect system. Here we establish communication between these two protocols using an AXI to OCP converter. This converter acts as a bridge between the two protocols clearing the incompatibilities for communication. We also use a clock bridge to enhance communication between IP blocks that operate at different frequencies. The numbers of masters, slaves, address and data widths are also configurable depending on the requirement. The AXI master, AXI to OCP converter, Clock Bridge, OCP master, OCP slaves, arbiter and address decoder are designed using VHDL and synthesized.


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