The data rate of 100 Mbps will be supported by upcoming 3G Long Term Evolution (LTE) standard. In 20 MHZ of bandwidth, this data rate will be attained. For the arrival of high data rate of the 3G LTE systems, there is an essential requirement of turbo decoder implementation. In this work, Log-MAP algorithm based turbo decoder for LTE receiver is proposed. The Log-MAP based turbo decoder provides performance nearer to Shannon’s limit with reasonable computational complexity. The VHDL coding for parallel architecture of turbo decoder using Log-MAP algorithm for LTE is simulated and synthesized using Xilinx XC3S200-4ft256, Spartan 3 family and the results are verified with the manual calculation.