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A Novel Custom Topology Generation for Application Specific Network-on-chip Using Genetic Algorithm Optimization Technique

Keywords: NoC , custom topology , genetic algorithm , low power , FPGA , ASNoC , ASIC

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In Networks-on-chips (NoC), the main sources of power consumption are global interconnection links and routers. In Application Specific NoC (ASNoC) power can be minimized by mapping the cores on the application specific topology (custom topology) rather than mapping on the standard topologies. In ASNoC, the design of the topology plays an important role in minimizing the power consumption and hop count. In this study, we propose a novel topology generation algorithm using genetic algorithm optimization technique to generate a custom topology for ASNoC architectures. We applied the proposed algorithm to six benchmark video applications MPEG 4 decoder, VOPD, MWD, mp3 audio encoder, mp3 audio decoder and DSP. The proposed topology generation algorithm achieves significant amount of power saving and decrease in the average number of hop count compared to the existing custom topology generation algorithms.


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