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Second-order sigma-delta modulator in standard cmos technology

DOI: 10.2298/sjee0403037m

Keywords: analog-to-digital conversion , sigma-delta modulation

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As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 μm technology.


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