This paper deals with SiGe HBTs optimization for power amplifier applications dedicated to wireless communications. In this work, we investigate the fT-BVCEO tradeoff by various collector optimization schemes such as epilayer thickness and dopant concentration, and SIC and CAP characteristics. Furthermore, a new trapezoidal base Germanium (Ge) profile is proposed. Thanks to this profile, precise control of Ge content at the metallurgical emitter-base junction is obtained. Gain stability is obtained for a wide range of temperatures through tuning the emitter-base junction Ge percent. Finally, a comprehensive investigation of Ge introduction into the collector (backside Ge profile) is conducted in order to improve the fT values at high injection levels. 1. Introduction SiGe heterojunction bipolar transistors (HBTs) integrated into BiCMOS technologies have been providing cost-effective solutions to many of the building blocks of RF and microwave transceivers. Power amplifiers have remained an exception to this trend for some time, but SiGe HBTs have emerged as competitive alternatives to III-V devices for RF power applications in wireless handsets and cell phones . State-of-the-art SiGe/Si HBTs dedicated to power amplifier application present a of 27？GHz with a BVCEO of 8.5？V . However, for similar breakdown voltages, the achieved Johnson’s limit using SiGe power HBTs and their power-handling capability per unit emitter area are not comparable with III-V power devices since the minority carrier mobility and the bandgap are lower in Si compared with III-V counterparts . To enhance SiGe HBTs performance in this field while maintaining its very competitive cost, further breakthrough in device design and optimization are mandatory. In this paper, we focused on three main SiGe HBTs features improvements: device robustness, temperature behavior and HF characteristics. The paper is organized as follows. First, process flow, RF power device structure and electrical device characteristics are illustrated. Results of static and dynamic performances are presented. Next, different optimization processes are described. These optimizations deal with collector tuning, Ge base profile engineering and Ge introduction into the collector layer. Finally, their impacts on the electrical characteristics are highlighted. 2. Device Structure Design and Fabrication Process 2.1. Process Flow Description This study has been carried out on the 250？nm SiGe HBT architecture shown in Figure 1, which consists in a double polysilicon quasi-self-aligned structure. Basically, the
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