The Analog-to-Digital-Converter (ADC) constitutes a necessary component for the implementation of Software – Defined- Radio (SDR) receiver. In ADC, sampling performance is limited by a clock. The sampling inserts the jitter noise, which degrades the performance of the receiver. Continuous–Time (CT) Delta–Sigma (ΔΣ) modulators arecapable of suppressing this noise but the impact of clock jitter at the output of the Digital– to–Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for analyzing jitter in SDR receivers when a CT–ΔΣ modulator is utilized for Analog–to–Digital Conversion (ADC).