This paper presents a development of a wideband delta-sigma modulator for fully digital GHz transmitters. The fully digital RF transmitter is developed as a promising solution for software defined radio (SDR) terminals and applications. The fully digital transmitter consists of a delta-sigma modulator, a high-speed multiplexer and a switching-mode power amplifier. The speed limitation of delta-sigma modulator is the main limitation to increase the signal bandwidth in fully digital transmitters. In this paper, the bandwidth of the fully digital transmitter is increased 8 times using parallel processing time-interleaved architecture, while maintaining the same signal quality. This architecture was implemented on FPGA and tested for different standards (WiMAX and LTE) with a signal bandwidth up to 8 MHz. The concept was assessed in terms of SNDR by using a differential logic analyzer at the output of FPGA, and the SNDR was found to be around 60 dB.