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An automatic hierarchical delay analysis tool
An Automatic Hierarchical Delay Analysis Tool

Keywords: 超大规模集成电路,性能分析,自动分层延迟分析工具,CAD

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The performance analysis of VLSI integrated circuits (ICs) with flat tools is slow and even sometimes impossible to complete. Some hierarchical tools have been developed to speed up the analysis of these large ICs. However, these hierarchical tools suffer from a poor interaction with the CAD database and poorly automatized operations. We introduce a general hierarchical framework for performance analysis to solve these problems. The circuit analysis is automatic under the proposed framework. Information that has been automatically abstracted in the hierarchy is kept in database properties along with the topological information. A limited software implementation of the framework, PREDICT, has also been developed to analyze the delay performance. Experimental results show that hierarchical analysis CPU time and memory requirements are low if heuristics are used during the abstraction process. This work is supported by grants from the Natural Sciences and Engineering Research Council (Canada) (NSERC) and the Ministry of Higher Education (Québec).


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