Basic CMOS VLSI Circuits and Low Power Devices Employing Various Reduction Techniques to Reduce Leakage Power at Low Supply Voltage in Nanoscale Technology
In this work, the author proposed various techniques for reducing leakage power, leakage current, power consumption and power supply voltage. In this work, we implement CMOS Inverter, NAND Gate, CMOS VLSI Based AOI-OAI Circuits and Full Adder. We also compare all implemented circuits with LECTOR Technique and LECTOR Stack State techniques, which are inserted between pull-up and pull-down network Proposed technique simulation has been performed using HSPICE software in 32 nm, 45 nm, 90 nm, and 180 nm nanometer technology with a supply voltage range of 0.6 V - 1.0 V. The battery life of modern mobile computing, multimedia, wireless communication, and other real-time applications is increasing with LECTOR and LECTOR stack state reduction (LSSR). According to HSPICE simulated results by CMOS Inverter, NAND gate, CMOS VLSI Based AOI-OAI circuits and full adder circuits, subthreshold leakage current is decreased by 89% compared to the base case, 80% compared to LECTOR, and 34% compared to LECTOR Stack state reduction method and LECTOR transistor. We can achieve better leakage reduction by controlling supply voltage and by making the switching CMOS transistor.
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