A Highly Parallel Area Efficient S-Box Architecture for AES Byte-Substitution

　 Abstract—The performance of the S-Box represents an important factor in the overall performance of the AES cryptography systems. It affects the speed, area, and the power consumption of the AES. In attempts to improve the performance of the S-box byte substitution a number of techniques were presented in the literature. In this paper, we classify the S-box byte substitution optimization techniques as those based on hardware, software, and combined hardware/software. We then move on to propose a new highly parallel and area-efficient S-box architecture for AES byte substitution. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area.