一种超低功耗的低压差线性稳压器环路补偿方法
A Loop Compensation Method of Low Dropout Regulator with Ultra Low Power

针对低压差线性稳压器(LDO)电路设计中为改善环路补偿的稳定性增加电流缓冲电路而带来额外功耗的问题,提出一种嵌入式LDO环路补偿方法。该方法在原LDO的误差放大器模块中,嵌入一个由晶体管和电容组成的电流缓冲电路,该结构与误差放大器的共源共栅输出级共用晶体管,由于整体电路中不增加新元器件,因此消除了引入缓冲电路所带来的额外功耗。仿真实验验证了加入电流缓冲电路后系统环路稳定性能得到了改善。采用联华电子公司0.5 μm 5 V的CMOS工艺线在LDO中进行了投片验证,实测芯片静态功耗电流仅为50 μA,当输入电压从3 V跳变到5 V时,输出电压的上冲与下冲都小于15 mV,负载电阻从18 kΩ跳变到9 Ω时,输出电压的最大变化小于20 mV。投片测试结果表明,该补偿方法可在提高系统环路稳定性的同时消除额外功耗。
An embedded loop compensation method of LDO is proposed to solve the problem that the current buffer technique overcomes the drawback of traditional miller compensation, but consumes extra power. It merges the current buffer into the fold？？back amplifier, so that the LDO circuit and the current buffer circuit share the transistor, and the loop stability of the circuit can be improved without adding the components. The principle of the proposed compensation method is analyzed and described in detail. The method is tested in a low？？dropout voltage regulator using UMC 0？？5 μm 5 V CMOS technology, and the results show that chip static power current has only 50 μA, and both the output voltage overshoot and undershoot are below 15 mV when the input voltage changes from 3 V to 5 V. The maximum change of the output voltage is less than 20 mV when the load resistance reduces from 18 kΩ to 9 Ω. The measurement results show that the embedded structure eliminates the extra power loss and improves loop stability