Landauer R.Irreversibility and heat generation in the computational process?s[J].IBM J. Res. Develop,1961,5(2):183-191 [2]Bennett C H.Logical reversibility of computation[J].IBM J. Res. Develop,1973,17(6):525-532 [3]Haghparast M and Navi K.A novel reversible full adder circuit for nanotechnology based systems[J].J. Appl. Sci,2007,7(24):3995-4000 [4] http://webhome.cs.uvic.ca/_dmaslov [5]Mohammadi M and Eshghi M.On figures of merit in reversible and quantum logic designs [C][J].Quant. Info. Process.,2009,8(4):297-318 [6] Parhami B. Fault tolerant reversible circuits[C]. Proc. 40th Asimolar Conf. Signals, Systems, and Computers. (Pacific Grove, CA,2006.10) 1726-1729 [7]lu Hongjun, Peng Fei, Wu Tianhao, et al.Irreversible logic operation accomplished by quantum reversible logic circuits[J].量子电子学报,2009,26(6):668-674 [8]Hagpharast M and Navi K.A novel fault tolerant reversible gate for nanotechnology based systems[J].Am. J. Appl. Sci,2008,5(5):519-523 [9]Islam M S.[J].Rahman M M , Begum Z, et al. Fault tolerant reversible logic synthesis: Carry Look-Ahead and Carry-Skip Adders[C]. IEEE Int. Conf. Adv. Comput.Tools Eng. Appl,2009,:- [10]Akbar E P A, Haghparast M and Navi K.Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology[J].Microelectron. J,2011,42(8):973-981 [11]Qi Xuemei, Chen Fulong, Zuo Kaizhong, et al.Design of fast fault tolerant reversible signed multiplier[J].,2012,7(17):2506-2514 [12]Haghparast M and Navi K.Novel reversible fault tolerant error coding and detection circuits[J].Int. J. Quant. Inform,2011,9(2):723-738
