A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters. 1. Introduction Today’s high-performance radar systems, such as SAR and AESA systems, exploit complex antenna arrays to perform the beam forming and steering functions by means of electronic control. Such systems are involved in a large variety of applications, both civilian and military in nature, or in research activities of scientific interest such as remote sensing and Earth observation. Such radar systems typically need a huge number of active radiating elements, each equipped with a Transmit/Receive (T/R) module. First examples of T/R modules [1, 2] consist of multifunction chips performing RF signal low noise and high power amplification, operating mode selection by RF switches, together with phase and amplitude signal conditioning. The latter functionalities, analog in nature, are digitally controlled, and the trend is toward increasing the resolution and the precision of the signal conditioning, attained by increasing the number of phase-shifting or attenuating cells. Such requirement naturally implies the increase in the number of digital controls to be fed into the single T/R module: for a typical 6-bit control (amplitude and phase) and separate architecture, the resulting number of bits is 13, leading to 26 digital lines (the required value and its opposite). Such high number of control lines for each module is typically generated by an on-board Silicon dedicated chip, wired to the GaAs analog functionalities and mounted/interconnected on an insulating substrate. The need for reducing T/R modules’ weight and size, led to the investigation for fully integrated
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