Low Power at Different levels of VLSI Design an clock Distribution Schemes

Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. In this paper various low power techniques at Gate level, Architecture level and different tradeoffs between different clock distribution schemes like as single driver clock scheme and distributed buffers clock scheme are reviewed. Here it is also tried to showing various effects of particular clock distribution scheme such as clock skew, clock jitter etc. Keywords: Algorithm level techniques, Circuit Level Aspects, Local restructing, Clock jitter, Clock skew.