ARITHMETIC COMPUTATIONS OF GALOIS FIELD IN MULTI- VALUED LOGIC

Binary number (0 and 1) is insufficient in respect to the demand of the coming generation. Multi- valued logic (with Radix >2) can be viewed as an alternative approach to solve many problems in transmission, storage and processing of large amount of information in digital signal processing. Multi-valued logic circuits have been offered as a solution to general interconnection and chip area problem. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. This Techno- logy leads to a decrease in number of inter- connections and resistance and capacitance of contacts and interconnections Here, in this paper Quaternary converter circuits are designed by using down literal circuits. Arithmetic operations like addition and multiplication in Modulo-4 arithmetic are per-formed by using multi-valued logic (MVL). Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. The proposed circuit is Galois addition and multiplication which requires fewer gates.Simulation result of each operation is shown separately using Tspice