Design of An Improved Block Cipher Reconfigurable Architecture
一种改进的分组密码可重构处理结构设计①

Coarse-Grained Reconfigurable Architecture aimed at cryptographic processing has been widely studied because of its good performance and flexibility. In a cipher reconfigurable processing architecture, a configuration circuit that has heigh efficiency can greatly reduce the configuration time and accelerate the accounting. In this paper, we improve the configuration circuit of a block cipher reconfigurable processing architecture and speed up the configuration of the block ciphers that have regular structure.