Design of high-speed multiplier based on standard cell library extension
基于标准单元库扩展的快速乘法器设计

This paper proposed a 17×17 bit signed digital multiplier. To improve the performance, the multiplier used modified Booth's recoding algorithm, a Wallace tree structure and design method based on standard cell library extension. It analyzed critical path using logical effort model, and by constructing cells with different driving capabilities, it implemented equal logical effort in each stage to achieve minimum path delay. Based on TSMC 90 nm standard cell library, generated an extended cell library, and implemented the layouts of multiplier respectively. Compared to standard cell library, the multiplier implemented with extended cell library achieved a performance improvement of 10.87%. Experimental results show that the semi-custom design methodology based on standard cell library extension can improve circuit performance effectively, which is especially appropriate for designs with large loads.