A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes
同步部分并行结构的准循环LDPC码译码器

Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper. In the decoder, the check node process units and variable node process units work concurrently, where the new generated soft information is used in advance during the iteration process to accelerate the convergence speed. Furthermore, differential evolution is utilized to optimize the start positions of node process units in order to achieve better performance. Simulation results show that the proposed scheme outperforms others both in performance and complexity, and is very suitable for the implementation of high speed decoders.