The Design of DPLL for Low SNR Signals with Large Frequency Offset
一种大频偏和低信噪比条件下的全数字锁相环设计

The digital phase-locked loops design is a key technology for carrier and bit synchronization in coherent demodulation digital receiver. Large frequency offset and low SNR add more difficulties of the loop design from two different ways. Based on this condition, aim at fast acquisition and tracking, a method of digital loop parameter algorithm is proposed in this paper and some useful conclusions are given.