An Efficient Implementation Architecture for Wideband Digital Downconversion
宽带数字下变频的一种高效实现结构

The wideband digital receiver systems require DDC with high speed and short tuning time in order to intercept narrowband signal in broad tuning bandwidth. However, these requirements can not be met by the commercial DDC. In this paper an efHcient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution of the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.