Design and optimization of a 2.4 GHz RF front-end with an on-chip balun
2.4GHz带片上非平衡变压器射频前端的设计与优化

In this paper, a 2.4GHz low-power, low-noise, and high linear receiver front-end with low noise amplifier (LNA) and balun optimization technique is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for best noise performance of the front-end. The circuit is implemented with 0.35um SiGe BiCMOS technology. The front-end has three gain steps for maximization of input dynamic range. The overall maximum gain is about 36dB. The double-sideband noise figure (DSB) is 3.8dB in the high gain (HG) mode, and the input referred third-order intercept point (IIP3) is 12.5dBm in the low gain (LG) mode. The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as output stage for test. The total front-end dissipates 33mw under 2.85-V supply and occupies 0.66mm2 die size.