Design of 700 V triple RESURF nLDMOS with low on-resistance
Design of 700V Triple RESURF LDMOS with Low On-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.