A Novel Combined Gated-Diode Technique for Extracting Lateral Distribution of Interface Traps in SOI NMOSFET
复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

A novel combined gated diode technique for extracting the lateral distribution of interface traps in SOI NMOSFET is presented.The key of this technique lies in the recombination generation (R G) current peak origination from the interface trap recombination is being modulated by the drain voltage of the combined forward gated diode architecture.The extraction principle is introduced in detail and the extraction procedure is also erected.The experimental results qualitatively show that the induced interface traps gradually decrease from the drain and source edges to the channel region while showing the highest value near both edges SOI in NMOSFET.