Switch-Level Timing Simulation Using RC Network as Delay Model
用RC网络作延迟模型的开关级定时模拟

A new method for switch-level timing simulation is proposed.We suggest that the timingsimulation should be performed by two steps.First,the future state is evaluated.Then,someRC networks are constructed to calculate signal delay.The issues on implementation of signaldelay calculation and construction of RC network delay model are discussed. A computer pro-gram LOMOS (LOgic simulator for MOS digital circuits) is developed.Experiments show thatLOMOS runs two to three orders of magnitude faster than SPICE with delay errors fallingwithin 30% usually.