%0 Journal Article
%T A Verilog HDL digital architecture for delay calculation
%A Chac¨®n-Rodr¨ªguez
%A A.
%A Mart¨ªn-Pirchio
%A F. N.
%A Juli¨¢n
%A P.
%A Mandolesi
%A P. S.
%J Latin American applied research
%D 2007
%I Scientific Electronic Library Online
%X a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] hz is presented. the method performs a delay calculation in order to determine the bearing angle of a sound source. computing accuracy is tested against a previous implementation of the cross correlation derivative method. a verilog rtl model of the method has been tested on a xilinx£¿ fpga in order to evaluate the real performance of the method. simulations of an asic design on a standard cmos technology predict a power saving of about 25 times per delay stage over previous implementations.
%K verilog
%K fpga
%K low power
%K digital cmos vlsi.
%U http://www.scielo.org.ar/scielo.php?script=sci_abstract&pid=S0327-07932007000100009&lng=en&nrm=iso&tlng=en