%0 Journal Article
%T Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio
%A Raja Mahmou
%A Khalid Faitah
%J World Journal of Engineering and Technology
%P 80-91
%@ 2331-4249
%D 2024
%I Scientific Research Publishing
%R 10.4236/wjet.2024.121005
%X This
work details the development of a broad-spectrum LNA (Low Noise Amplifier)
circuit using a 65<span><span><span style=\"font-family:;\" \"=\"\"> </span></span></span><span><span><span style=\"font-family:;\" \"=\"\">nm CMOS technology. The design incorporates an inductive degeneracy
circuit, employing a theoretical approach to enhance gain, minimize noise
levels, and uphold low power consumption. The progression includes a shift to a
cascode structure to further refine LNA parameters. Ultimately, with a 1.8</span></span></span><span><span><span style=\"font-family:;\" \"=\"\"> </span></span></span><span><span><span style=\"font-family:;\" \"=\"\">V bias,
the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5
dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This
architecture is adept at operating across a wide frequency band spanning from
0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.</span></span></span>
%K LNA
%K Degeneracy
%K Noise Figure
%K Linearity
%K Power Consumption
%K Gain
%U http://www.scirp.org/journal/PaperInformation.aspx?PaperID=130760