%0 Journal Article
%T 用反相器实现积分的低压低功耗级联型ΔΣ调制器<br>A Cascaded ΔΣ Modulator with Low Voltage and Low Power Using Inverter for Integration
%A 李吉军
%A 张瑞智
%A 孙权
%A 张鸿
%J 西安交通大学学报
%D 2018
%R 10.7652/xjtuxb201808017
%X 针对传统级联型ΔΣ调制器中运算放大器(OTA)增益要求过高和功耗过大的问题,提出了一种用反相器实现积分的级间反馈级联型低压低功耗调制器。该调制器采用带有级间反馈的级联型结构,从系统上消除了传统级联结构中传递函数失配的风险,大大降低了模拟积分器的设计要求,不再需要高电源电压、高增益的OTA实现积分来保证传递函数的精确性。此外,采用低增益、低功耗的C类反相器实现积分功能,节约了芯片功耗和面积,用0.5 μm互补型金属氧化物半导体(CMOS)工艺设计了一个两级级联的四阶ΔΣ调制器,仿真结果表明,所设计的调制器版图核心面积仅为858 μm×525 μm,调制器可工作在低至1.4 V的电源电压下,在信号带宽为3.9 kHz、过采样率为128的情况下,信噪失真比(SNDR)最大为99.8 dB,平均电流消耗仅为58.6 μA。该调制器适用于低频信号的高精度处理,具有低压低功耗优势。<br>A cascaded ΔΣ modulator with low voltage and low power using inverter for integration is presented to solve the requirement for high？？supply voltage and high？？gain operational transconductance amplifiers (OTA) in integrators. The cascaded structure with interstage feedback circumvents the mismatch problem in conventional cascaded structure, and reduces the design demands of analog integrators, without need of high？？gain OTA under high supply voltage for the accuracy of the transfer function. A two？？stage cascaded fourth？？order ΔΣ modulator is designed using 0.5 μm complementary？？metal？？oxide？？semiconductor (CMOS) process, and class？？C inverters are utilized for integration to reduce power consumption and chip area. Simulation results under a supply voltage as low as 1.4 V show that the proposed modulator achieves 99.8 dB peak signal？？to？？noise？？plus？？distortion？？ratio (SNDR) and 58.6 μA current consumption in the case of an oversampling ratio of 128 and a 3.9 kHz signal bandwidth, while the modulator only occupies a chip area of 858 μm×525 μm. The proposed modulator has advantages of low supply voltage and low power consumption, and is suitable for high？？resolution processing of low？？frequency signals
%K 反相器
%K 低压
%K 低功耗
%K 级联型结构
%K ΔΣ调制器&lt
%K br&gt
%K inverter
%K low voltage
%K low power
%K cascaded structure
%K ΔΣ modulator
%U http://zkxb.xjtu.edu.cn/oa/DArticle.aspx?type=view&id=201808017