%0 Journal Article
%T A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer
%A Kenichi Ohhata
%A Kaihei Hotta
%A Naoto Yamaguchi
%A Daiki Hayakawa
%A Kenji Sewaki
%A Kento Imayanagida
%A Yuuki Sonoda
%J Circuits and Systems
%P 1-13
%@ 2153-1293
%D 2017
%I Scientific Research Publishing
%R 10.4236/cs.2017.81001
%X This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.
%K Time-Based ADC
%K Flash ADC
%K TDC
%K VTC
%K CMOS
%U http://www.scirp.org/journal/PaperInformation.aspx?PaperID=73350