%0 Journal Article
%T 脑电可穿戴无线射频发射芯片系统的研究<br>Research of Brain EEG Wireless Radio Transmitter IC System for Wearable Application
%A 孙建辉
%A 刘军涛
%A 王蜜霞
%A 徐声伟
%A 蔡新霞
%J Optoelectronics
%P 39-46
%@ 2164-5469
%D 2016
%I Hans Publishing
%R 10.12677/OE.2016.62007
%X <div style=\"text-align:justify;\">
	<span style=\"line-height:1.5;\">针对脑电EEG (electroencephalograph)传感网络近距离无线传输与可穿戴应用的需要，给出了一款无线射频电路控制系统：集成了模拟电路(8通道低噪声脑电放大器与中速SAR-ADC模数转换)、信道编码EEG-DSP加速器、射频发射芯片。在ISM-2.4 GHz波段，射频物理层使用射频直接上变频架构，通过FSK/OOK (on-off-keying)的数据调制方式；重点优化基于PLL的频率综合器(PLL-FS)与可开关的E类功率放大器(PA-E)；PLL-FS具有低相位噪声(？119 dBc/Hz@1 MHz)、锁定时间短(28~60 us)、环路特性好的特点；PA优化了输出功率(4~5 dBm)、功率增加效率PAE(25%)、S-参数等。流水EEG-DSP负责整体系统控制、数据缓存、精简无线信道编码以及输出码流调制射频电路。设计利用Cadence Co.的SpecterRF软件、Synopsys Co.的系列数字软件/Caliber软件进行了功能仿真/物理版图验收，设计使用SmicRF180 nm数模混合工艺进行了加工，流片回来的测试结果表明EEG-DSP与射频发射芯片可以满足实际应用。<br />
Focus on the brain EEG (electroencephalograph) transducer network short range transmitting and wearable application, the design gives an integrated wireless controlling system which is composed by analog circuit (eight-channel EEG low-noise amplifier and intermediate speed SAR-ADC), wireless channel coding EEG-DSP accelerator, low-power and robust radio frequency chip. At the ISM-2.4 GHz frequency band, the radio frequency chip uses the radio frequency di-rect-up-conversion architecture, with FSK/OOK data modulation method. The design has opti-mized the frequency synthesizer based on PLL, the PA’s outputting power (4 - 5 dBm), PAE (power added efficiency: 25%), S-Parameters have been optimized too. The pipeline EEG-DSP is responsible for the whole system’s controlling, data storage, reduced wireless channel coding and bit-stream outputting. The design uses the Cadence Co’s SpectreRF, Synopsys Co.’s serial logic-design tools, Caliber Co.’s tool to complete the function verify/physical layout signoff. These chips have been manufactured by the SmicRF180 nm analog/digital mixed technology, and the back’s chips test results show that the EEG-DSP and RF chip’s critical parameters satisfy the expected proposed requirements.</span><span style=\"line-height:1.5;\"></span> 
</div>
%K 脑电EEG，数模混合芯片设计，FSK/OOK，射频直接上变频，相位噪声，DSP流水硬件加速器<br>Brain EEG
%K Mixed Analog/Digital IC Design
%K FSK/OOK
%K Radio Frequency Direct-up-Conversion
%K Phase Noise
%K Pipeline DSP Hardware Accelerator
%U http://www.hanspub.org/journal/PaperInformation.aspx?PaperID=17751