%0 Journal Article
%T The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
%A Chi Wai Yu
%A Julien Lamoureux
%A Steven J. E. Wilton
%A Philip H. W. Leong
%A Wayne Luk
%J International Journal of Reconfigurable Computing
%D 2008
%I Hindawi Publishing Corporation
%R 10.1155/2008/736203
%X This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.
%U http://www.hindawi.com/journals/ijrc/2008/736203/