%0 Journal Article
%T Scalable Successive-Cancellation Hardware Decoder for Polar Codes
%A Alexandre J. Raymond
%A Warren J. Gross
%J Computer Science
%D 2013
%I arXiv
%R 10.1109/TSP.2014.2347262
%X Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.
%U http://arxiv.org/abs/1306.3529v1