%0 Journal Article
%T Scalable RFCMOS Model for 90£¿nm Technology
%A Ah Fatt Tong
%A Wei Meng Lim
%A Choon Beng Sia
%A Xiaopeng Yu
%A Wanlan Yang
%A Kiat Seng Yeo
%J International Journal of Microwave Science and Technology
%D 2011
%I Hindawi Publishing Corporation
%R 10.1155/2011/452348
%X This paper presents the formation of the parasitic components that exist in the RF MOSFET structure during its high-frequency operation. The parasitic components are extracted from the transistor's S-parameter measurement, and its geometry dependence is studied with respect to its layout structure. Physical geometry equations are proposed to represent these parasitic components, and by implementing them into the RF model, a scalable RFCMOS model, that is, valid up to 49.85£¿GHz is demonstrated. A new verification technique is proposed to verify the quality of the developed scalable RFCMOS model. The proposed technique can shorten the verification time of the scalable RFCMOS model and ensure that the coded scalable model file is error-free and thus more reliable to use. 1. Introduction The relentless scaling down of CMOS technologies has greatly improved the RF performance of MOSFET. It has been reported that for a technology node of 90£¿nm, high of 209£¿GHz and of 248£¿GHz are achieved [1]. Furthermore, the scaling down of the transistor has brought about lower , and it is now comparable to the reported SiGe BJT process [1, 2]. The improved RFCMOS performance coupled with its lower cost has motivated circuit designers to integrate digital, mixed-signal, and RF transceiver blocks into a single chip [3¨C7]. However, for these RF chips to operate at higher-frequency region, the circuit design specifications will become more stringent, and this will require accurate and scalable RFCMOS models that can be simulated accurately at high-frequency region. Furthermore, by employing scalable RF CMOS model into the process design kit (PDK), the circuit design environment is improved, and this can help circuit designers in their circuit optimization and shorten the design cycle and time to market of these RF chips. Most of the RF models developed today are based on the macromodelling approach. In this approach, subcircuit components are added to the transistor¡¯s core model to model the RF parasitic of MOSFET structure [8, 9], and the core model used is usually the commercially available models such as BSIM3v3 [10] and BSIM4 [11]. The subcircuit components are extracted from the measured S-parameters of the transistor, but the extracted values of these RF components can differ when different extraction technique is used. All the existing RF parameter extraction technique is based on the transistor¡¯s small-signal equivalent circuit analysis. Therefore, to characterize an RF MOSFET, all its RF parasitic elements must be included into the small-signal equivalent circuit.
%U http://www.hindawi.com/journals/ijmst/2011/452348/