%0 Journal Article
%T 高速双相动态电路暨设计自动化流程之实现<br>A Fully Synthesizable Design Flow for High-Speed Dual-Phase Domino Logic
%A 蔡佑慈
%A 黄翔晖
%A 郑经华
%J Open Journal of Circuits and Systems
%P 23-29
%@ 2327-0861
%D 2013
%I Hans Publishing
%R 10.12677/OJCS.2013.22005
%X <div style=\"text-align:justify;\">
	<span style=\"line-height:1.5;\">由于骨牌逻辑电路通常较互补式金氧半组件电路计具有较小的面积与更快的速度，所以已经被广泛使用于设计高速电路如微处理器的设计中。虽然有许多关于动态电路的研究，然而大部份的研究却忽略探讨如何实现其研究成果。在本论文中，我们设计了一个创新的双相操作高速动态电路，它具有管线式</span><span style=\"line-height:1.5;\">(pipeline)</span><span style=\"line-height:1.5;\">的电路结构，运作速度不受电路复杂度的影响，使得它的效能较传统动态电路的提升极多，因具容忍频率歪斜</span><span style=\"line-height:1.5;\">(skew tolerant)</span><span style=\"line-height:1.5;\">的特性，可使用标准组件之设计流程来设计。最后，芯片测量结果证明完成了下述设计目标：一个</span><span style=\"line-height:1.5;\">Performance Scalable</span><span style=\"line-height:1.5;\">的</span><span style=\"line-height:1.5;\">very high speed dynamic 32 </span><span style=\"line-height:1.5;\">×</span><span style=\"line-height:1.5;\"> 32 bits</span><span style=\"line-height:1.5;\">之</span><span style=\"line-height:1.5;\">multiplier</span><span style=\"line-height:1.5;\">具有下列特性：</span><span style=\"line-height:1.5;\">1) </span><span style=\"line-height:1.5;\">高速频率操作，工作效能较一般传统动态电路改善甚多。</span><span style=\"line-height:1.5;\">2) </span><span style=\"line-height:1.5;\">可以为容忍</span><span style=\"line-height:1.5;\">clock skew</span><span style=\"line-height:1.5;\">，使用</span><span style=\"line-height:1.5;\">Duty Cycle Pulse Generator (DCPG)</span><span style=\"line-height:1.5;\">的技术来产生</span><span style=\"line-height:1.5;\">double clocking</span><span style=\"line-height:1.5;\">的时间，可借由</span><span style=\"line-height:1.5;\">DCPG</span><span style=\"line-height:1.5;\">来克服</span><span style=\"line-height:1.5;\">process variation</span><span style=\"line-height:1.5;\">及</span><span style=\"line-height:1.5;\">cell based design clock tree routing</span><span style=\"line-height:1.5;\">所造成的</span><span style=\"line-height:1.5;\">skew</span><span style=\"line-height:1.5;\">的问题。</span><span style=\"line-height:1.5;\">3) </span><span style=\"line-height:1.5;\">使用</span><span style=\"line-height:1.5;\">BIST</span><span style=\"line-height:1.5;\">技术作为正常效能的自测功能，此功能可转为本芯片在</span><span style=\"line-height:1.5;\">process</span><span style=\"line-height:1.5;\">后仍可以调整电路效能，做为电路</span><span style=\"line-height:1.5;\">performance management</span><span style=\"line-height:1.5;\">的机制。</span><span style=\"line-height:1.5;\">&lt;br/&gt;</span><span style=\"line-height:1.5;\">Domino logic design offers smaller area and higher speed than complementary CMOS design. Domino logic design has become a very popular technology used to design high-performance processors. There have been several studies conducted on dual phase operation dynamic circuit, but most have focused on theory without practical imple-
%K 双相动态电路；管线式动态电路<br>Dual-Phase Dynamic Circuit
%K Pipeline Dynamic Circuit
%U http://www.hanspub.org/journal/PaperInformation.aspx?PaperID=11947