%0 Journal Article
%T Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA
%A Tayab Memon
%A Paul Beckett
%A Amin Z. Sadik
%J ISRN Electronics
%D 2012
%R 10.5402/2012/538597
%X In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based area-performance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance. 1. Introduction It is no surprise that many signal processing tasks can be accomplished by a microprocessor or a digital signal processor (commonly called DSP kits). Built-in multiplication modules are the core element of these devices. Furthermore, implementation of multiply and accumulate (MAC) circuits within signal processors can significantly improve the throughput of FIR and IIR digital filters structures (see Figures 1 and 2) that require a large number of multiply and accumulation operations per a sampling period. Figure 1: General structure of FIR filter. Figure 2: Block Diagram of an IIR direct form II filter. An alternative solution is to use gate-level programmable devices such as field programmable gate arrays (FPGAs) to perform the digital filtering tasks. Concurrent (i.e., parallel) mode of operations of these devices is of great interest as it can improve the throughput of the digital signal processing circuits especially digital filtering modules. This higher throughput can be achieved at the cost of a higher chip area compared to the serial implementation of the circuits. Many of these FPGA devices include a number of built-in multipliers that take up a large amount of silicon area within the device. Further, the most recent FPGA devices include resources that easily support general purpose signal processing tasks even within mid-range commercial devices. However, there is a direct tradeoff between chip area and throughput in these devices. Some obvious applications that require fast and efficient digital filters are decimation filters, audio filter banks, charge-coupled-device filters, and software defined radio, all of which
%U http://www.hindawi.com/journals/isrn.electronics/2012/538597/