%0 Journal Article
%T Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits
%A Kirti Gupta
%A Neeta Pandey
%A Maneesha Gupta
%J ISRN Electronics
%D 2012
%R 10.5402/2012/529194
%X Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18£¿¦Ìm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented. 1. Introduction Digital VLSI circuits can be broadly classified into synchronous and asynchronous circuits. A synchronous circuit employs a common clock signal to provide synchronization between all the circuit components. The synchronous circuits suffer from the problems of clock distribution and clock skew which becomes a challenge to overcome as the technology scales down. Asynchronous circuits, on the other hand, are attractive replacements to synchronous designs as they perform synchronization through handshaking between their components. Some other advantages of asynchronous circuits include high speed, low power consumption, modular design, immunity to metastable behavior, and low susceptibility to electromagnetic interference [1]. Traditionally, the asynchronous circuits were implemented by using CMOS logic style but due to the substantial dynamic power consumption at high frequencies, CMOS logic style is usually not preferred. MOS Current Mode Logic (MCML) is found to be an alternative to the CMOS asynchronous circuits in the literature [2¨C5]. A conventional MCML circuit consists of a differential pull-down network (PDN), a current source, and a load. The PDN implements the logic function, the current source generates the bias current , while the load performs the current to voltage conversion [6]. The circuit has static power consumption given as the product of the supply voltage and the bias current. The power consumption can be lowered by either reducing the bias current or the supply voltage. The reduction in bias current is generally not favored as it degrades the speed [7]. Therefore, lowering the supply voltage of the circuit is preferred. One of the techniques suggested in [8, 9] is multithreshold MOS Current Mode Logic (MT-MCML) which uses multithreshold transistors in conventional MCML circuits. In this paper, MT-MCML technique has been applied to implement
%U http://www.hindawi.com/journals/isrn.electronics/2012/529194/