%0 Journal Article
%T A 0.6-V to 1-V Audio Modulator in 65£¿nm CMOS with 90.2£¿dB SNDR at 0.6-V
%A Liyuan Liu
%A Dongmei Li
%A Zhihua Wang
%J VLSI Design
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/353080
%X This paper presents a discrete time, single loop, third order modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65£¿nm CMOS, the modulator achieves 95£¿dB peak SNDR at 1-V supply with 24£¿kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2£¿dB under 0.6-V low supply. The total power dissipation is 371£¿¦ÌW at 1-V and drops to only 133£¿¦ÌW at 0.6-V. 1. Introduction CMOS technology has progressed into sub-100£¿nm era. Advanced technology offers speed power and area benefits for digital circuits design. However the sub 1-V low supply voltage, reduction of intrinsic gain, deteriorated device matching, and dramatic increase of flicker noise have brought difficulties to precision analog designs [1]. The modulator is a popular building block which is strongly demanded in high accurate analog signal conditioning such as digital audio. Several designs have been reported with sub-100£¿nm technology. Although large dynamic range has been achieved, the SNDR performance is lower than 80£¿dB due to large flicker noise and high harmonic distortion [2¨C5]. In [4, 5], continuous time modulator (CT-DSM) is adopted for low power implementation. Although the bandwidth requirement of the amplifier is relaxed in CT-DSM than that in discrete-time modulator (DT-DSM), CT-DSMs suffer from problems such as sensitivity to clock jitter, performance degradation due to excessive loop delay, and needing tuning circuits to deal with RC time constant variations. In this work, we propose a high performance DT-DSM. The feedforward path together with multibit quantizer leads to very small swings at integrators¡¯ outputs. Both gain and bandwidth requirements of amplifiers are relaxed. To overcome large area and power dissipation problems associated with traditional flash multibit quantizer and conventional analog summing, in this work we propose a self-timing successive approximation (SAR) quantizer with embedded analog summing circuitry. The prototype modulator is fabricated in 65£¿nm CMOS. Measurement shows that peak signal to noise and distortion ratio (SNDR) of 95£¿dB is achieved across 24£¿kHz under 1-V with 371£¿¦ÌW. Under 0.6-V supply, the
%U http://www.hindawi.com/journals/vlsi/2013/353080/