%0 Journal Article
%T LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization
%A Tinoosh Mohsenin
%A Houshmand Shirani-mehr
%A Bevan M. Baas
%J VLSI Design
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/913018
%X An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65£¿nm CMOS. A 5.10£¿mm2 low power decoder implementation achieves 85.7£¿Gbps while operating at 185£¿MHz and dissipates 16.4£¿pJ/bit at 1.3£¿V with early termination. At 0.6£¿V the decoder throughput is 9.3£¿Gbps (greater than 6.4£¿Gbps required for 10GBASE-T) while dissipating an average power of 31£¿mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35£¿dB at . 1. Introduction Communication systems are becoming a standard requirement of every computing platform from wireless sensors, mobile telephony, netbooks, and server class computers. Local and cellular wireless communication throughputs are expected to increase to hundreds of Mbps and even beyond 1£¿Gbps [1¨C3]. With this increased growth for bandwidth comes larger systems integration complexity and higher energy consumption per packet. Low power design is therefore a major design criterion alongside the standards¡¯ throughput requirement as both will determine the quality of service and cost. Additionally, mobile computing will take on a new dimension as a portal into Software as a Service (i.e., cloud computing) where low performance computers can tap into the power of a distant high-performance computer cluster [4, 5]. So far the emerging 10GBASE-T standard has not been adopted as quickly as predicted into the data center infrastructures because of their power consumption [6]. The power consumption of the 10GBASE-T PHY layer (more specifically the receiver, whose implementation is left open by the 802.3£¿an standard [7]) has become difficult to reduce [8]. LDPC code was first developed in 1962 [9] as an error correction technique that allowed communication over noisy channels possibly near the Shannon limit. With advancements in VLSI, LDPC codes have recently received a lot of attention because of their superior error correction performance and have been adopted by many recent standards
%U http://www.hindawi.com/journals/vlsi/2013/913018/