%0 Journal Article
%T Faster and Energy-Efficient Signed Multipliers
%A B. Ramkumar
%A Harish M. Kittur
%J VLSI Design
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/495354
%X We demonstrate faster and energy-efficient column compression multiplication with very small area overheads by using a combination of two techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using new hybrid adder structures proposed here. Based on the proposed techniques, 8-b, 16-b, 32-b, and 64-b Wallace (W), Dadda (D), and HPM (H) reduction tree based Baugh-Wooley multipliers are developed and compared with the regular W, D, H based Baugh-Wooley multipliers. The performances of the proposed multipliers are analyzed by evaluating the delay, area, and power, with 65£¿nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multipliers are as much as 29%, 27%, and 21% faster than the regular W, D, H based Baugh-Wooley multipliers, respectively, with a maximum of only 2.4% power overhead. Also, the power-delay products (energy consumption) of the proposed 16-b, 32-b, and 64-b multipliers are significantly lower than those of the regular Baugh-Wooley multiplier. Applicability of the proposed techniques to the Booth-Encoded multipliers is also discussed. 1. Introduction High-speed multiplication is a primary requirement of high-performance digital systems. In recent trends, the column compression multipliers are popular for high-speed computations due to their higher speeds [1, 2]. The first column compression multiplier was introduced by Wallace in 1964 [3]. He reduced the partial product of rows by grouping into sets of three-row set and two-row set using (3,2) counter and (2,2)£¿£¿counter, respectively. In 1965, Dadda altered the approach of Wallace by starting with the exact placement of the (3,2) counter and (2,2) counter in the maximum critical path delay of the multiplier [4]. Three-dimensional minimization- (TDM-) based column compression approach was proposed in 1996 to perform fast multiplication [5]. Since the 2000s, a closer reconsideration of Wallace and Dadda multipliers has been done and proved that the Dadda multiplier is slightly faster than the Wallace multiplier and the hardware required for Dadda multiplier is lesser than the Wallace multiplier [6, 7]. The HPM-based column compression was developed in 2006, and it has standard layout structure than Eriksson et al.¡¯s multiplier [8]. The detailed case for HPM-based Baugh-Wooley multiplier against the Booth-Encoded multipliers has been described in [9]. In this work, we implement the proposed techniques with
%U http://www.hindawi.com/journals/vlsi/2013/495354/