%0 Journal Article
%T Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic
%A Shipra Upadhyay
%A R. K. Nagaria
%A R. A. Mishra
%J VLSI Design
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/726324
%X Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 ¡Á 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18£¿¦Ìm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50£¿MHz and 300£¿fF external load capacitance in comparison to CMOS and QSERL circuits. 1. Introduction With increased scaling in CMOS technology, modern designs are capable of performing very high speed computations as the complexity, and the number of devices on a given IC is no longer an issue. Much of the research efforts in the recent decades have been dedicated to improving the speed of digital systems. Thus, high speed computation has become an expected norm for average users. Higher switching activities lead to higher power consumption. Many methodologies have been proposed so far [1] which intended to reduce power consumption, among them adiabatic logic technique [2] is promising alternative. Concept of adiabatic logic circuits is generated from the adiabatic process which is a thermodynamically reversible process that is operated slowly, so that total energy dissipation tends towards zero. Energy dissipated in a circuit depends on how fast the circuit switches or charges and discharges which means that it depends on the approach taken to design the circuit. When the rate of charging will be lower, less amount of energy is drawn from the source. Adiabatic circuits also have another mechanism for energy saving [3] that is based on recovering the energy stored in nodal capacitances. The quality factor of any adiabatic process is also known as degree of
%U http://www.hindawi.com/journals/vlsi/2013/726324/