%0 Journal Article
%T FPGA-Based Fixed Point Implementation of a Real-Time Induction Motor Emulator
%A L. Charaabi
%J Advances in Power Electronics
%D 2012
%I Hindawi Publishing Corporation
%R 10.1155/2012/409671
%X This paper investigates the numerical issue of a discrete-time induction-motor emulator implementation. The stability analysis of the finite-word-length implementation shows a coupling between required word length and the sample rate. We propose specific guidelines to analyze this coupling and to estimate the required data word length for both signals and coefficients of the model. To respect algorithm requirements, an FPGA-based implementation was used for architecture development. The direct torque control is implemented to verify in real time the AC-motor emulator prototype. 1. Introduction Control algorithms of electrical drives are usually tested by the attachment of electrical motors. Experimental testing requires direct measuring by employing measurement instrumentation and sensors that would be complex, impractical, noise sensitive, and expensive. Traditionally these tests are performed on motor and inverter models under software simulation environments which are, in most cases, non-real-time and unable to exactly replicate real operational conditions. In order to provide a real-time verification of the implemented control algorithm and increase the realism of simulation, the control algorithm is tested while connected to a real-time emulator for the plant (induction motor and inverter) [1]. Due to their high capacities of executing in real-time complex algorithm, FPGA technology is a good candidate for this kind of RT emulator [2]. For reasons of cost, simplicity, speeds and memory space, the real-time emulator of the induction motor is performed with the Euler¡¯s shift discretization method and quantized with fixed point format [3]. The robustness of the discretized algorithm is a critical issue in fixed-point format implementation. It is well known that, stable, closed-loop system may become unstable when the algorithm is implemented using a fixed-point processor due to finite-word-length effects. The fractional part precisions in fixed point are chosen to guarantee a minimum signal-to-noise ratio for finite-word-length quantization effects. The integer part is computed using norms [4]. In an FPGA implementation, it is possible to use separate fixed-point format for each coefficient and signal in the algorithm. Hence, the use of FPGA allows maintaining a higher computational precision at critical points. In this paper, authors propose a real-time induction motor emulator designed in fixed point format for an FPGA implementation. The starting point is a continuous-time model. Discrete-time models are derived using the traditional shift form
%U http://www.hindawi.com/journals/ape/2012/409671/