%0 Journal Article
%T Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell
%A Vandna Sikarwar
%A Saurabh Khandelwal
%A Shyam Akashe
%J Chinese Journal of Engineering
%D 2013
%R 10.1155/2013/738358
%X Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated- technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45£¿nm technology. 1. Introduction CMOS scaling has led to improvement in performance of digital circuits however faces significant challenges due to process technology limits. Short-channel effects, subthreshold leakage, gate dielectric leakage, and device-to-device variations are the leading challenges in additional leakage current. Scaling to nanometer regime produces a major short-channel effect which arises from several geometrical effects in which the channel length becomes equal to the depletion layer. Drain-induced barrier lowering (DIBL) is the major effect produced by SCE, in which high electric fields from the drain can lower that barrier that is supposedly only controlled by the gate. As technology scales down, while dealing with short-channel effects (SCEs), not only very ultrathin to keep the current drive is required but also very low is required to maintain the device speed and variations under control [1] as this effect can degrade the devices subthreshold slope and cause changes in the threshold voltage ( ). Leakage current produced due to SCE is mainly categorized into two types. They are gate leakage and subthreshold leakage. The subthreshold current generally occurs when the gate-to-source voltage of transistors is less than the threshold voltage . When the current flows from the gate through the oxide layer to substrate, this current is called gate leakage current. As we go down below 65£¿nm technology, there seems to be no viable options of continuing forth with the conventional MOSFET. Therefore, multigate FETs such as planar double-gate FETs and FinFETs have been proposed for low-power digital
%U http://www.hindawi.com/journals/cje/2013/738358/