%0 Journal Article
%T Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA
%A Salman Sadruddin
%A Arshad Aziz
%J Chinese Journal of Engineering
%D 2013
%R 10.1155/2013/453872
%X A novel and highly efficient design of a software defined radiation tolerant baseband module for a LEO satellite telecommand receiver using FPGA is presented. FPGAs in space are subject to single event upsets (SEUs) due to high radiation environment. Traditionally, triple modular redundancy (TMR) is used for mitigating Single Event Upsets (SEUs). The drawback of using TMR is that it consumes a lot of hardware resources and requires more power. Reduced precision redundancy (RPR) can be a viable alternative of TMR in digital systems for arithmetic operations. This paper uses the combination of RPR and TMR for mitigating SEUs. The designed module consumes less resources on FPGA and has bit error rate (BER) identical to theoretical results, apart from degradation due to implementation losses. An improved Costas loop and timing recovery algorithm are implemented for achieving carrier recovery and bit synchronization. The hybrid approach mitigates SEUs while consuming 26% less resources than a customary TMR protected receiver. 1. Introduction Reconfigurability and adaptability are one of the most desirable features of modern space technology. FPGA provides this flexibility along with good performance. They have become an integral part of satellite systems for over a decade. Their high computational capacity combined with small size and light weight makes them a preferable choice over other digital systems. The ability to reconfigure FPGA with an updated functionality reduces the hardware requirement in space craft [1]. However, FPGAs face some severe problems in the space environment. The high energy particles in space may interact with memory cells within an integrated circuit and can change their logic state [2]. This alteration may disrupt the operation of a digital system defined by memory cells. FPGAs contain large array of memory cells which makes them more susceptible to single event upsets (SEUs). In order to operate properly in space, some mitigation techniques need to be applied in FPGAs. Traditionally, triple modular redundancy (TMR) has been used for this purpose. The drawback of using TMR is that it consumes a lot of hardware resources and requires more power [3]. Thus, there has been a constant effort to find an alternative to the TMR technique. Shim and Shanbhag [4] introduced reduced precision redundancy (RPR) as part of a power-reduction technique for ASIC-based systems; Snodgrass [5] demonstrated variation of RPR on FPGA to limit high magnitude errors of arithmetic operations in high radiation environment. Pratt et al. [6] have presented the
%U http://www.hindawi.com/journals/cje/2013/453872/