%0 Journal Article
%T Physical Scaling Limits of FinFET Structure: A Simulation Study
%A Gaurav Saini
%A Ashwani K Rana
%J International Journal of VLSI Design & Communication Systems
%D 2011
%I Academy & Industry Research Collaboration Center (AIRCC)
%X In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap andTriple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. Toanalyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness,fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length(L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. DrainInduced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goesbelow 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off currentratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found thatboth fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be moredominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratiodecreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. Therelative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current perunit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
%K Double Gate
%K Triple Gate
%K Underlap
%K Overlap
%K FinFET
%K High performance (HP)
%K ITRS
%U http://airccse.org/journal/vlsi/papers/2111vlsics03.pdf