%0 Journal Article
%T NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS
%A Subodh Wairya
%A Rajendra Kumar Nagaria
%A Sudarshan Tiwari
%J International Journal of VLSI Design & Communication Systems
%D 2011
%I Academy & Industry Research Collaboration Center (AIRCC)
%X This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logicfamily. The objective of this work is to present a new full adder design circuits combined with current modecircuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majorityfunction based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventionalstatic and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a highdegree of regularity and symmetric higher density than the conventional CMOS design style as well aslower power consumption by using bridge transistors. This technique helps in reducing powerconsumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmodelogic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over staticCMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against thereported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay,power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18¦Ìmprocess models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage andsimulations are carried out on Spectre S.
%K Full adder
%K Majority-Not gate
%K Dynamic circuits
%K MOSCAP
%K Power-delay product (PDP)
%K Very Large Scale Integrated (VLSI) Circuits
%K Current mode logic
%K Hybrid XOR-XNOR circuit
%K Bridge full adder.
%U http://airccse.org/journal/vlsi/papers/2211vlsics07.pdf